1. Field of the Invention
This invention relates generally to memory structure, and, more specifically, to architectures for storing and retrieving multi-byte instructions.
2. Background Information
In a microprocessor, instructions and other data are transferred between the memory and the CPU along a data bus of a size fixed by the microprocessor""s architecture. The amount of data that can be supplied in a single fetch operation is determined by this bus size. The microprocessor will also have addressing circuitry, usually employing a separate bus, for designating the location of the data to be fetched.
One example of a memory often found on a microprocessor is the one time programmable (OTP) memory. This is usually a relatively small memory such, as an EPROM, in which the instructions for the microprocessor""s particular application are programmed. Although most of this discussion is more general, many of the described problems are more acute in the OTP example due the limited size of this memory and the frequency with which it is used.
As the complexity of tasks to which microprocessors are applied has increased, the number of instructions needed have correspondingly increased. This number of instructions frequently cannot be accommodated within the available number of instruction that can be constructed out of one or two bytes. Consequently, it has become increasingly common for the instruction set to include three byte instructions. As the standard data bus for supplying these instructions is usually one or two bytes wide, the processor must perform multiple fetches to retrieve a three-byte instruction.
This subjects the memory to some very stringent access requirements. For example, consider the case of a microprocessor that supports single, double, and triple byte instructions with an internal bus width of the memory data word is 16 bits. If the instruction set had just included single or double byte instructions, then a single 16-bit memory access could provide the code word, whether single or double byte, for program executions. This access could just occur once per machine cycle time and not be a strain on the memory circuitry or process technology. However, if three byte instructions are an integral part of the architecture, it is necessary for the user to perform two 16-bit memory accesses per machine cycle in order to retrieve a three-byte instruction. Consequently, the required memory access speed will be at least halved relative case when only one and two byte instructions are required.
This problem is further aggravated when the machine uses instructions that vary in length between one and three bytes. This produces the problem of how to retrieve the correct number of bits and not waste memory space. For example, with a three-byte instruction in an architecture with a 16-bit bus, two 16-bit memory fetches would provide 32 bits of data when only 24 bits are needed for the instruction. The additional eight bits in memory would be wasted since the next 16-bit access could not begin on an eight bit word boundary.
The present invention could be expanded to applications for any number of bytes, but for ease of illustration the invention will be based upon performing a single 24-bit memory fetch, which allows the user to access all three bytes of a maximum length instruction simultaneously. This access needs only to occur once per machine cycle, thereby relaxing of the memory requirements. This access relaxation makes it easier to design the memory, will allow a lower power design, prolongs the usability of the process technology, or enable us to increase the physical memory size while maintaining performance. The present invention also incorporates instructions that are a single or double byte wide without any degradation in performance or wasted physical memory space. For single byte instructions, the primary byte is accessed along with the next two bytes in the address sequence. The processor knows up-front that a single-byte instruction is being accessed and ignores the two other bytes that are presented. A two-byte instruction fetch is performed in a similar way, with 24 bits with the first two bytes (16 bits) being the instruction and the remaining single byte being the next instruction in the address sequence. The processor knows it is accessing a two-byte instruction and accepts the data while disregarding the remaining byte of the three-byte access.
To achieve this operation, the exemplary embodiment divides the memory block into two xc3x9716 memories with the second memory having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these xc3x9716 memories, the full address is provided. If the address is within the two columns of the second xc3x9716 memory, the full address is also provided to the second xc3x9716 memory. If the address is to the first of the xc3x9716 memories, the second xc3x9716 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte. The net effect is that all the physical memory physical space is used for program code with none being wasted in the 24-bit access.